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TLA6400

로직 애널라이저

가격 대비 놀라운 성능을 제공하는 혁신적인 디지털 디버그 솔루션

TLA6400 시리즈 로직 애널라이저는 디지털 시스템의 기능을 디버깅, 검증, 최적화하는 데 필요한 성능을 경제적인 가격으로 제공합니다. 또한 TLA6400 시리즈는 포착하기 어렵고 찾기 힘든 문제를 신속하게 격리, 식별, 특성화할 수 있는 포괄적인 신호 무결성 디버깅 도구 집합을 제공합니다. 여기에 최신 애플리케이션에 대한 광범위한 지원이 추가되어, 현재 디지털 설계의 모든 디버깅 과제에 대응하는 이상적인 도구를 확보할 수 있습니다.
27~30일 내 배송

Tektronix TLA6400 Series logic analyzers provide a significant price-performance breakthrough for digital debug.

Features and benefits
  • Performance and ease of use to debug, validate, and optimize digital systems
    • 40 ps resolution MagniVu™ Acquisition to accurately see signal relationships in your system
    • State Speed - Sample your fastest synchronous buses with clock rates up to 667 MHz and data rates up to 1333 Mb/s
    • 15 in. display, with optional touch screen to see more of your data and navigate efficiently through your data
    • 4 models with 34/68/102/136 channels and up to 64 Mb record length offer flexible solutions to fit any budget
    • Drag-and-Drop Triggering - Simply drag any one of eight different trigger types from a table to the waveform and the TLA will automatically set up the trigger conditions. Eliminates errors, improves repeatability, and saves time.
    • Drag-and-Drop measurements - Simply drag an icon from the measurement toolbar and drop it on your signal of interest and get a table of results. Saves time, removes complexity, and reduces measurement uncertainty.
  • Comprehensive set of signal integrity tools that allow you to quickly isolate, identify, and debug complex signal integrity issues
    • Glitch Trigger and Storage - Allows you to trigger on and highlight potential signal integrity problems. Not only can the TLA6400 Series trigger on the problem, but by highlighting suspected problems in red, you will easily determine which signals you need to investigate further.
    • iCapture -Route the suspected signal to the analog output of the TLA6400 Series using the exclusive Tektronix iCapture feature. This eliminates the need to double-probe with an oscilloscope probe, reducing time to debug.
    • iView - Time-correlated view of both logic analyzer and oscilloscope data to trace the SI problem across the digital and analog domain.
Applications
  • Digital hardware validation and debug
  • Monitoring, measurement, and optimization of digital hardware performance
  • Embedded software integration, debug, and verification

Efficiently debug and validate your digital system at a price you will like!

The affordable TLA6400 Series logic analyzers offer the performance needed to debug, validate, and optimize the functionality of your digital system. The TLA6400 Series provides a comprehensive set of signal integrity debug tools that allow you quickly isolate, identify, and characterize elusive and hard-to-find problems. Add a broad range of support for today's applications, and you have the ideal tool to help you meet all of the debug challenges of today's digital designs.

The TLA6400 Series allows you to effectively validate and debug the functionality of your digital designs:

  • Use the patented 25 GHz MagniVu technology to accurately measure timing relationships. The single, integrated acquisition architecture of the TLA6400 Series eliminates the timing skew problems inherent in other logic analyzer architectures.
  • Capture buses with clock rates up to 667 MHz and data rates up to 1333 Mb/s.
  • Buy the capability you need now and upgrade as your measurement needs grow.
  • Quickly isolate events through a simple and intuitive drag-and-drop trigger setup.
  • Easily summarize your design's performance with sophisticated drag-and-drop measurements such as frequency, period, pulse width, duty cycle, and edge count.
  • View data in a variety of time-correlated formats including waveform, listing, graph, disassembly, source code, or compare.

 

Oscilloscope integration

The TLA6400 seamlessly integrates with Tektronix oscilloscopes to make it easy to find problems that cross between the digital and analog portions of a design.

Probing

The TLA6400 with iCapture can be used as flexible and convenient probe system for your oscilloscope. It allows you to use one probe for both your logic analyzer and your oscilloscope eliminating the need to double-probe signals. With a single probe, you can view both the digital and analog characteristics of the signal.

You can route up to four analog signals through the TLA6400's 2 GHz analog mux to your oscilloscope and change the signals you are viewing with just a mouse click. This eliminates the need to physically move an oscilloscope probe to make a new measurement

Display and triggering

In addition to integrated probing, iView allows time-correlated logic analyzer and oscilloscope waveforms to be integrated into a single TLA6400 waveform window simplifying viewing and analysis. You can also trigger the oscilloscope from the logic analyzer or have the oscilloscope trigger the logic analyzer.

The connection between the TLA6400 and the oscilloscope consists of two BNC cables for cross triggering and a data connection to transfer data between the instruments. The data connection can be GPIB, USB, or a LAN connection.

This seamless integration not only helps you troubleshoot functional issues in your design, but also helps you find signal integrity problems caused by crosstalk, termination mismatches, ground bounce, and other issues.

Use the TLA6400's glitch trigger to monitor selected signals in your design and trigger when a signal integrity problem is found on any one of these signals. Signals with suspected signal integrity problems can also be tagged allowing you to quickly identify the signals of interest.

The analog nature of the suspected signals can then be routed to an oscilloscope using the exclusive iCapture functionality and viewed in the TLA6400 using iView.

DDR2/DDR3 and LPDDR2 memory validation

A complete DDR2/DDR3 and LPDDR2 protocol debug and validation solution is available for the TLA6400. This tool set consist of everything embedded engineers - even those who are not DDR experts - need to validate and debug the operation of memory sub-systems in their designs.

Support consists of a set of tools designed to provide visibility to all address, data, and control signals and consists of:

  • Memory chip and PoP (Package-on-Package) interposers that provide a convenient way of probing embedded DDR memory systems and eliminates the need to design in probe access points. These interposers work with the unique iCapture Analog Mux feature of the TLA6400 to provide a single probing solution for both the logic analyzer and oscilloscope, saving time and minimizing setup complexity.
  • Setup software to configure the TLA6400 to accurately sample the DDR signals.
  • Protocol decode software that shows all of the DDR transactions as well as providing triggering on DDR events.
  • Optional protocol violation software that finds and reports any violation of the JEDEC-defined DDR protocol.

 

The DDR protocol debug and validation solution supports:

  • x4, x8, and x16 DDR2 devices up to speeds of DDR2-1333.
  • x4, x8, and x16 DDR3 devices with speeds up to DDR3-1333.
  • LPDDR2 PoP devices with speeds up to LPDDR2-1333.

 

DDR2/DDR3 protocol debug and validation solutions
  DDR2 memory

Up to DDR2-1333 (667 MHz clock) state measurements on Addr/Cmd/Data. 1

DDR3 memory

Up to DDR3-1333 (667 MHz clock) state measurements on Addr/Cmd/Data. 1

x4/x8 Configurations Requires 68 channel model or higher (Option 1T required for DDR2-800, DDR2-1067, and DDR2-1333) Requires 68 channel model or higher (Option 1T required for DDR3-800, DDR3-1067, and DDR3-1333)
Memory Chip Interposer 2: NEX-DDR2MP60BLASK (socketed) or NEX-DDR2MP60BLA (non-socketed) Memory Chip Interposer 3: NEX-DDR3MP78BLASK (socketed) or NEX-DDR3MP78BLA (non-socketed)
NEX-PRB1XL64 (requires 2)
NEX-PRB1XL64 (requires 2)
NEX-PRB1XL64 (requires 2).
(Optional) Protocol software: NEX-DDR-PROTOCOL (Optional) Protocol software: NEX-MCATLA-DDR3-SWL
x16 Configurations Requires 68 channel model or higher (Option 1T required for DDR2-800, DDR2-1067, and DDR2-1333) Requires 68 channel model or higher (Option 1T required for DDR3-800, DDR3-1067, and DDR3-1333)
Memory Chip Interposer 2 : NEX-DDR2MP84BLASK (socketed) or NEX-DDR2MP84BLA (non-socketed) Memory Chip Interposer 3 : NEX-DDR3MP96BLASK (socketed) or NEX-DDR3MP96BLA (non-socketed)
NEX-PRB1XL64 (requires 2) NEX-PRB1XL64 (requires 2)
(Optional) Protocol software: NEX-DDR-PROTOCOL (must be ordered directly from Nexus) (Optional) Protocol software: NEX-MCATLA-DDR3-SWL
LPDDR2 protocol debug and validation solutions
  LPDDR2 Memory

Up to DDR2-1333 (667 MHz clock) state measurements on Addr/Cmd/Data. 4

168 Ball Package on Package (x32 Data Width) Requires 68 channel model or higher (Option 1T required for LPDDR2-800, LPDDR2-1067, and LPDDR2-1333)
Memory Chip Interposer: NEX-LP2POP168BLASK 5 (Socketed)
NEX-PRB1XL64 (requires 2)
(Optional) Protocol software: NEX-MCATLA-LP2-SWL
216 Ball Package on Package (2x32 Data Width) Requires 68 channel model or higher (Option 1T required for LPDDR2-800, LPDDR2-1067, and LPDDR2-1333)
Memory Chip Interposer: NEX-LP2POP216BLASK 5 (Socketed)
NEX-PRB1XL64 (requires 2)
(Optional) Protocol software: NEX-MCATLA-LP2-SWL

1 All configurations support simultaneous capture of Read and Write data.

2 DDR2 Memory Chip Interposers include Sample Point Analyzer Tool (SPA), Logic Analyzer configuration files, and DDR Protocol Decoder and Triggering Support.

3 DDR3 Memory Chip Interposers include Sample Point Analyzer Tool (SPA), ICIS Software, Logic Analyzer configuration files, and DDR Protocol Decoder and Triggering Support.

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