Key performance specifications

• PCI Express Gen1, Gen2, and Gen3 Protocol to Physical Layer Analysis for link widths from x1 through x16 with up to 8.0 GT/s acquisition rates.
• Industry's deepest 8 GB memory/module (16 GB memory, x16 link width) increases the chances of capturing an error and the fault that caused the error.

Key features

• Comprehensive PCI Express probing solutions, including midbus, slot interposer, and solder-down probes.
  • Nonintrusive probing that uses OpenEYE technology incorporating automatic tuning equalization circuitry to allow probing anywhere on the channel and ensures accurate data capture in PCI Express systems with channel lengths up to 24 in. and two connectors.
  • Single-click calibration process calibrates the analyzer and probes to the target BER. Calibration results for analyzer/probe sets are remembered from one session to another.
  • ScopePHY provides the ability to quickly connect any of the PCI Express midbus, slot interposer, or solder-down probes to a high-performance oscilloscope providing a more detailed analog view of the PHY Layer.
• Shorten time to gain confidence in the test system setup.
  • Front-panel LEDs provide status information such as link speed, symbol lock, and link activity.
  • Auto-configure sets up the logic protocol analyzer system to be ready for data acquisition quickly.
  • FastSYNC tracks the Link as it transitions in and out of ASPM Power states such as L0s, regardless of electrical Idle duration.
  • Real-time statistics help observe link health and behavior over time.
• Powerful trigger-state machine spans all layers of the protocol.
  • 8 States
  • 8 Packet recognizers
  • 4 Symbol sequence recognizers
  • 4 Counter/Timers
  • 4 Event flags
  • Conditional storage
  • Real-time filtering
• HW accelerated search and data displays provide immediate visibility of data regardless of record length.
• Information density for rapid data analysis
  • The Transaction window provides visibility into protocol behavior at the packet and transaction level interspersed with physical layer activity.
  • Innovative Bird's Eye view provides a high-ground visibility of system issues involving flow control.
  • The Summary Profile window helps ascertain the health of the system and identify patterns of interest such as errors, TLPs, DLLPs, ordered sets.
• Multibus visibility for system-level debug
  • Analyze complete system interactions with time-correlated, multibus analysis on a single display on a single mainframe. For example, tracing memory access from PCI express to DDR memory or monitor multiple PCIe links on a PCIe switch.
  • Cross Triggering and a common global time stamp enables accurate and efficient debugging by showing exactly what was happening on one bus relative to another at any given instant in time.

The TLA7SA00 series logic protocol analyzer Setup window provides a quick overview of link connection status.

TLA7SA16 Logic Protocol Analyzer module.

Applications

• PCI Express debug from Protocol layer to Physical layer
  • Silicon validation
  • Computer system validation
  • Embedded system debug and validation
• Processor/Bus debug and verification
• Embedded software integration, debug, and verification

PCI Express debug and analysis spanning Physical to Transaction-layer with feature-rich hardware

PCI Express 3.0 introduces new challenges for validation engineers. Time-to-market pressures require a solution that can quickly pinpoint problems. The TLA7SA00 Series logic protocol analyzer modules provide an innovative approach to PCI Express validation that spans all layers of the protocol from the Physical layer to the Transaction layer.

Reduce the time to information by viewing and searching up to 16 GB deep memory in just seconds with rapid display updates enabled by our industry-leading hardware acceleration.

Features such as auto-training, auto-tracking, front-panel LED lane status, single-click calibration, allow the logic protocol analyzer to "wire" itself automatically which shortens the time it takes for users to build confidence in the test system.

Quickly trigger on patterns of interest with powerful trigger capabilities that span across all protocol layers. Real-time filtering provides the ability to filter unwanted data and use the acquisition memory more efficiently by storing only transactions of interest.

Elusive power state anomalies pertaining to entry into and exit from electrical idle and ASPM states such as L0s to L0 are easily addressed by FastSYNC technology. It ensures quick re-synchronization of the logic protocol analyzer with the PCI Express FTS ordered sets regardless of the duration of electrical Idle time. This capability is unique compared to other solutions where the L0s to L0 re-synchronization time is specified only over a short electrical idle time of 2 μs or less.

Innovative data displays for accelerated time to information

The new PCI Express software helps view information in a hierarchical and rich format. Protocol information can be expanded and collapsed to rapidly display or hide information as needed.

Quickly ascertain the health of the system and identify patterns of interest (errors, specific transactions, ordered sets) with statistical summary and data graphs using the Summary Profile window. Summary statistics include useful information such as average transaction latency, total bytes transmitted, and bus utilization.

Summary Profile window

Protocol behavior can be viewed at the packet and transaction level interspersed with physical layer activity in a single innovative Transaction window. The Transaction Stitching feature shows packets participating in a completed transaction or incomplete transactions as errors in a diagrammatic representation. Additional capabilities, including color coding of the packets, cursor locking across multiple data windows, and a unique Bird's Eye view integrated with the Transaction window provides a high-ground visibility of system issues involving flow control.

Transaction window with integrated Bird’s Eye view

Further insight into physical layer details can be gained with the unique Listing window showing packet details and lane-by-lane symbol decode. You can also view individual lane activity correlated with analog waveforms from your high-bandwidth oscilloscope in the Waveform window.

Listing window showing packet details and lane-by-lane symbol decode

Waveform window showing individual lane activity correlated with analog waveform

Hardware developers, hardware/software integrators, and embedded system designers will appreciate the tight integration with the Tektronix logic analyzer. This provides visibility of complete system interactions with time-correlated, multi-bus analysis on a single display. Cross triggering and a common global time stamp enables accurate and efficient debugging by showing exactly what was happening on one bus relative to another at any given instant of time.

High-performance PCI Express probing solutions for different application needs

The P67SA00 Series probes provide validation engineers with a comprehensive set of PCI Express probing solutions, including midbus, slot interposer, and solder-down connectors. With support for PCI Express Gen1, Gen2, and Gen3 channel lengths up to 24 in. with two connectors, these probes use OpenEYE technology offering minimal electrical loading with the highest signal fidelity and active equalization to ensure accurate data recovery of closed eyes. All P67SA00 Series probes feature a graphical lane-swizzling capability for maximum flexibility to accommodate unique circuit board layouts.

P67SA01SD – single differential input PCI Express solder-down probe, shown with Option 1P power adapter.

P67SA16S – x16 PCI Express Slot Interposer probe. (x8, x4, x1 Slot Interposer probes also available)

P67SA16 – x8 PCI Express Midbus probe and accessories. (x4 Midbus probe also available)

With ScopePHY, quickly connect any of the probe connector outputs to an oscilloscope using the P67UHDSMA probe lead set to gain further insight into the PHY layer. Tektronix-supplied S-parameters of the probe and module configure the DSP filters of Tektronix oscilloscope to show the PCI Express link data eye at the probe tip.

P67UHDSMA – x2 PCI Express probe lead set for P67SA00 probe connections to oscilloscopes.